Control circuit for generating output signal of specified duration at specified delay after receiving input signal

ABSTRACT

A control system for turning on and off an apparatus which discharges a coating liquid onto objects at a coating station. A sensor positioned adjacent the path of the objects upstream of the coating station initiates an interval timer as an object passes. After a predetermined time delay, the timer turns on a discharge gun positioned at the coating station, to begin to deposit the liquid upon the object. The timer maintains the discharge gun in an actuated condition for a predetermined time duration, and then turns the gun off. The control provides rapid and reliable turn on and turn off of the coating apparatus without false triggering, and provides precise time intervals which are continuously settable over an exceptionally wide range. The control utilizes a rapid reset hold and lock out circuit, SCR switches, unijunction relaxation oscillators having constant current charging circuits, an over voltage output circuit with short circuit protection, and means for programming the operation of plural discharge devices over different time periods.

United States Patent Algeri et al.

[ Nov. 27, 1973 CONTROL CIRCUIT FOR GENERATING OUTPUT SIGNAL OF SPECIFIED Primary Examiner-Stanley D. Miller, Jr. DURATION AT SPECIFIED DELAY AFTER y Herron & Evans RECEIVING INPUT SIGNAL [75] Inventors: Harvey R. Algeri, North Olmstead; [57] ABSTRACT Robert E. Sandorf, Canton, both of Ohio A control system for turning on and off an apparatus which discharges a coating liquid onto objects at a [73] Assignee: Nordson Corporation, Amherst, coating station. A sensor positioned adjacent the path Ohio of the objects upstream of the coating station initiates an interval timer as an object passes. After a predeter- [22] Flled' 1972 mined time delay, the timer turns on a discharge gun [21] Appl. No.: 241,455 positioned at the coating station, to begin to deposit the liquid upon the object. The timer maintains the Related Apphcat'on Data discharge gun in an actuated condition for a predeter- DIVISIOH Of SCI. NO. Jan. 20, Pat. NO. mined time duration and then turns the gun ff: The control provides rapid and reliable turn on and turn off of the coating apparatus without false triggering, [52] US. Cl 307/293, 307/265, 307/283, and provides precise time intervals which are comimb 307/284' 307/288 328/130 ously settable over an exceptionally wide range. The [51] IIII. CI. I H03k 17/26 control utilizes a rapid reset hold and lock out circuit [58] Fleld of Search 288, switches, unijunction relaxation oscillators 307/283 328/72 75 129-131 ing constant current charging circuits, an over voltage output circuit with short circuit protection, and means [56] References C'ted for programming the operation of plural discharge de- UNITED STATES PATENTS vices over different time periods.

3,319,086 5/1967 Yee 307/288 0 3,350,688 /1967 Kasper et al.. 340/167 x 12 Claims, 6 Drawmg Figures 3,381,088 4/1968 Lentz et al.... 307/288 X 3,391,389 7/1968 Cruger et al.. 307/288 X 3,532,907 lO/l970 Kasper 307/293 7' .7. Z T; 2%;? 5i .149 74 i mm 76 ,w

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58/ mki= 5w 7 7/ 4/; A534 15% 583 -2 a 41 55;? 4d,? 4,; 65 552 1 I /9 L402 302 7'0 M71756, 06 F158 5M K aaw/r/M 2, 503 is l 1 3 PATENIED H Z 1975 3,775 624 sum 2 OF 5 PATENTED NUV 2 7 i975 SHEET 3 OF 5 CONTROL CIRCUIT FOR GENERATING OUTPUT SIGNAL OF SPECIFIED DURATION AT SPECIFIED DELAY AFTER RECEIVING INPUT SIGNAL This is a division of application Ser. No. 108,082, filed Jan. 20, 1971, now US. Pat. No. 3,682,131, issued Aug. 8, 1972.

The present invention relates to coating apparatus controls and, more particularly, to automatic controls for timing the operation of the discharge of coating liquid upon objects as they are moved in relation to the discharge nozzle of the coating apparatus.

In coating systems of many types, series of objects are moved sequentially in relation to a coating station from which a coating liquid is discharged from one or several discharge nozzles and deposited upon the objects as they move past the station. In paint spray systems, for example, series of objects are carried past a paint spray station upon a moving conveyer. At the station, decorative and protective coating liquids such as paints, varnishes, waxes, etc. are sprayed upon the objects.

Another type of coating system is one in which adhesive, such as hot melt adhesive, is discharged upon objects as they are sequentially fed past the discharge apparatus. One typical application of the hot melt adhesive system is one in which the adhesive is deposited upon pre-cut paper carton blanks, as they are advanced toward a folding apparatus wherein they are to be folded and glued into the shapes of cartons. Another typical use of hot melt adhesive systems of this type lies in systems in which the adhesive is applied to a base object as it is being fed to an apparatus which positions another object such as a liner against the adhesive coated portion of the base object, as, for example, in the application of disc linings to bottle caps.

Another important application of such coating systems is in the spraying of protective coatings upon cans which are to be used as beverage containers or the like. In such applications, partially formed cans are guided along a predetermined path into a position at a coating station adjacent a coating apparatus. At the coating station a discharge apparatus is actuated to deposit the coating, usually in the form of a spray, upon the inside or the outside or both inside and outside, of the can.

In such coating systems, controls are employed to intermittently actuate the discharge apparatus so that the coating liquid is deposited only upon a specified portion of the objects when the objects are at some predetermined position in relation to the discharge station. Typically, such controls are synchronized to the relative position of the moving objects to be coated in relation to the discharge station. This synchronization usually is achieved by providing a sensor which senses the presence of an object in relation to the discharge station, either directly or indirectly, directly by sensing the presence of the object itself, and indirectly by sensing the presence of the conveyer means or machine element which moves in accordance with the motion of the object. This sensor is most conveniently positioned upstream of the coating station and is connected through a time delay device to control the operation of the discharge device. The time delay device accounts for the time lag between the sensing of the object and the positioning of the object at the coating station. In many cases, an additional timing function is provided to control the duration of the discharging operation.

Varying conditions, such as varying shapes and sizes of the objects to be coated, varying response times of the discharge apparatus due to differing types of coatings of varying viscosities, and a wide range of system operating speeds, make it desirable that the delay and duration time intervals be variable to accommodate these changing conditions. Furthermore, in order that the coating be deposited on precisely the desired portion of the object, high precision and accuracy in the settings of these time intervals is important to provide a proper coating and to prevent waste of the coating liquid.

Such control systems, for example, must incorporate timers which operate in a time range which is relatively long in terms of electronic circuit time constants, but which is relatively short in terms of the operating and switching times of the coating apparatus operated. Such time ranges lie within the range of from one millisecond to several seconds, for example. The control system must provide a rapid and positive turning on and turning off of the coating discharge apparatus while providing accurate control of the time intervals between operations of the spray system. In addition, the control system must be insensitive to signals from the sensor which represent anything other than a specific point on the workpiece moving relative to the coating station. Usually, this point which the sensor is to respond to is the leading edge of the object or workpiece on a conveyer, or to some specific point on the mechanism which moves with the object. However, due to irregularities in the workpieces themselves and to environmental noise sources, several signals can be generated by a sensor in addition to the signal responsive to the desired point to be sensed. This is especially true of photocells, limit switches and proximity switches which make up the most convenient types of sensors. Such'erroneous signals, unless discriminated from the desired signal from the sensor, can result in costly and wasteful operation of the coating apparatus.

These features are particularly important in such high speed systems as hot melt systems and can coating systems.

In the hot melt systems, for example, blank cartons may be fed past a discharge station at speeds of 200 feet per minute or higher. The hot melt discharge apparatus operates to deposit adhesive in narrow strips from a fraction of an inch to several inches in length upon the carton blanks as they are fed past the station. In these systems, it is extremely important that the discharge nozzle open and close at precisely the beginning and end of the region which is desired to be coated, not only so that the product has the proper adhesive applied to it, but so that excessive application of adhesive is avoided. Improper application of adhesive can result in defective cartons, while excessive adhesive results in undue cost of the cartons.

In can coating systems, for example, cans are coated in various ways on machines which operate sequentially upon several hundred cans per minute. In some applications, the cans are traversed linearly past stationary spray devices which might apply coating, for example, to the welded seams of the cans. In other applications, the cans are moved into position adjacent the spray devices where they are stopped and then rotated while the coating is sprayed on the inside through the open ends of the cans. In the latter application, for example, the can is sensed as it is fed into position adjacent the discharge device, sometimes indirectly by a sensing of the motion of the feed device. A time delay is required in order to allow the can to be stopped in its proper position and then rotatably accelerated to a uniform velocity before the coating can be applied. The duration of the application of the coating must be precisely controlled in order to insure that the coating is applied to the interior of the can uniformly by operating the discharge gun for an integral number of revolutions of the can, with allowance for only a very slight overlap. In this way, the minimum coating thickness can be precisely maintained while wasted coating material due to excessive overlap is eliminated.

In the high speed hot melt systems, one application in which the timing is highly critical is that of applying hot melt to the inside of bottle caps, so that linings or gaskets can be secured inside them. In this application, only a very small amount of glue is deposited and the duration of the discharge operation might be in the area of 34 milliseconds or less. In such cases, it is essential that the drop of hot melt be deposited precisely at the right instant as the caps are positioned adjacent the nozzle. Typically, this accuracy must be within plus or minus one millisecond, while the delay time from the instant the cap is sensed may be from 15-20 milliseconds or longer.

For these high speed applications, the timers provided by the prior art systems for this purpose have not provided precision and reliability with continuous time interval settings over a sufficiently wide range of settings. Furthermore, many prior art coating system timers have not been completely insensitive to erroneous trigger signals, or have not reset quickly enough to respond to the sensing of the next successive object.

Accordingly, the present invention is predicated in part upon the concept of providing a bi-stable trigger circuit which will rapidly respond to the first signal from the sensor generated by the detection of an object moving relative to the coating station, to lock out further input signals until completion of the coating operation, at which time the trigger circuit is rapidly reset so that the next object will be detected. The present invention is further predicated in part upon the concept of providing a delay-duration interval timer which operates in conjunction with the trigger circuit to rapidly and positively switch between ready, delay and duration conditions. Furthermore, the timers which provide these features must also have the capability of varying the time intervals to any length within an exceptionally wide range of time intervals.

The timer incorporates unijunction relaxation oscillators, with constant current charging circuits, operating in a one-shot capacity in combination with bi-stable SCR switches. In addition, the present invention is predicated in part upon providing a solenoid driver circult which operates to rapidly energize, hold and deenergize the solenoids of the coating apparatus control system, but which does not delay the operation and resetting of the control circuit which operates more rapidly than the solenoids can respond, and which further provides output short circuit protection.

Another aspect of the present invention is a provision for the combining of general timing controls to operate plural discharge devices, and in the further provision for programming the timer outputs to operate the different discharge devices over different periods of time during the coating cycles.

One basic advantage of the present invention is that it provides a higher reliability and more rapid operation of a coating apparatus, in intermittently coating workpieces moving relative to the coating station, than do the systems of the prior art, and overcomes the disadvantages of prior art systems set forth above.

These and other objects and advantages of the present invention will be more readily apparent from the following detailed description of the drawings illustrating one preferred form of a control for a coating apparatus according to principles of the present invention, wherein:

FIG. 1 is a diagrammatic view partially in perspective of a hot melt coating system embodying principles of the present invention;

FIG. 2 is a schematic diagram of a portion of the control circuit of the system of FIG. 1 illustrating particularly the trigger circuit;

FIG. 3 is a schematic diagram of a portion of the control circuit of the system of FIG. 1 illustrating particularly the timing circuit;

FIG. 4 is a schematic diagram of a further portion of the control circuit of the system of FIG. I illustrating particularly the output circuit and the power supply circuit; and

FIGS. 5 and 6 are partial block and partial schematic diagrams illustrating plural timer controls for the system of FIG. I, and including means for programming the outputs.

SYSTEM DESCRIPTION AND OPERATION Referring to FIG. 1, a coating system illustrated is of the type in which hot melt adhesive is deposited upon paperboard carton blanks which are to be folded into cartons. In such a system, a conveyer 10 represents the means by which a plurality of cartons or workpieces 11 are sequentially fed and carried in a prescribed path past a coating station 20. The conveyer 10 moves at some predetermined speed. In high speed hot melt systems, the conveyer travels at a speed of two hundered feet per minute or higher. At the coating station 20, a discharge apparatus such as a hot melt gun operates to discharge a coating of liquid adhesive upon the workpieces 11 as they move successively past the coating station 20. The coating apparatus at the station 20 includes a hot melt source 21 having an output port 22 connected to a pump 23 which advances the melt to a delivery line 24. Connected to the delivery line 24 are one or more remotely controllable check valves 25 which, in the embodiment shown, are solenoid controlled check valves. Each of the check valves 25 connects the line 24 to a discharge nozzle 27. The nozzles 27 are directed toward the conveyer l0 and operate to discharge a strip of hot melt 28 upon the workpieces 11 as they are advanced past the station 20. At the station 20, the check valves 25 open intermittently so that the hot melt is only discharged on the desired portions of the workpieces 11 when they are adjacent the coating station 20. The time period for which the valves 25 remain open constitues the duration of the coating interval. During this interval, the leading edge of the workpiece 11 travels through a distance D with the conveyer 10. In many paint-spraying and can coating applications, the check valves 25 are opened to start the spray just before the leading edge of the workpiece 11 enters the station 20, and remains opened until the trailing edge of the workpiece 11 passes the station 20. In such applications, the distance D is as long as the objects 11. In the hot melt application illustrated, the

adhesive is applied only to a portion of the length of the objects 11 and the distance D is in this case less than the length of the object.

To provide control for timing the coating interval, the illustrated embodiment of the present invention provides a sensor unit 40 positioned adjacent the conveyer l0 upstream of the coating station 20. The sensor unit 40 has provision for mounting various types of sensors which are responsive in various ways to the presence of a workpiece 11 at a position 41 along the conveyer adjacent the sensor 40. In the preferred embodiment the sensor 40 is a photocell adapted to generate a signal in response to the leading edge of the workpiece 11 as it moves past the sensor 40. The outputs 44 of the sensor 40 are connected to the inputs of an OR- gate 45 which has its output 46 connected to the input 51 of a control circuit 50. The output 52 of the control circuit 50 is connected in turn to the input 81 of a solenoid driver amplifier 80 which has its output 82 connected to the windings of the solenoid controlled check valves 25 to energize the solenoids and thereby turn on the gun for the duration of the coating interval. Because the sensor 40 is positioned upstream of the station 20, the coating interval must be delayed for the amount of time required for the leading edge of the workpiece 11 to move from the sensor 40 to a position 42 adjacent the coating station 20. During this delay, the leading edge of the object 11 moves through a distance D The control circuit 50 provides this timing operation through a trigger circuit 60 and a delay-duration timer circuit 70. The trigger circuit 60 has an input 61 connected to the control circuit input 51 and operates to develop a trigger signal from the sensor 40 and apply it at its output 54 to the input 55 to the timing circuit 70, while locking out erroneous signals from the sensor. The timing circuit 70 is energized by the trigger signal to activate the amplifier 80 after a delay interval, then to de-activate the amplifier 80 after a further duration interval, and to reset the trigger lock out circuit at the end of the duration interval.

The sensor 40 may be any one of a number of devices, and the specific embodiment of the present invention is designed to provide a selection of general sensor devices. Preferred for many applications is a photocell sensor which is connected so that it may develop a sensor signal either upon the making or upon the breaking of a light beam. Other sensors provided include limit switches positioned along the conveyer to be tripped by the workpiece 11, for example by the leading edge of the workpiece 11, as it passes upon the conveyer. The switches provided include both normally opened or normally closed switches. Provision for another sensor, such as a proximity switch sensor or some other type of sensor adapted to generate a positive going electrical signal, can also be used with the present invention. The present invention provides an input selector gate 45 having a plurality of inputs connected to the outputs 44 of the different types of sensors. The selector gate 45 has its output 46 connected to the input line 51 of the control circuit 50. This input 51 connects to the input 61 of the trigger circuit 60.

The trigger circuit input 61 connectsthrough a differentiator 63 to one input of an OR-gate 64. Another input of the OR-gate 64 is connected to the output of an AND-gate 65 which has another one of its two inputs connected to output of the OR-gate 64. This provides a feedback circuit 66 which operates as a holding circuit to lock the OR-gate 64 to the ON condition when a sensor pulse is received from the sensor 40. To turn the holding circuit 66 off, a reset circuit 67 is pro vided connected between the output of a differentiator 68 and a negative input of the AND-gate 65. The input of the differentiator 68 is connected to the reset input 53 of the trigger circuit 60. When a positive going electrical signal appears at the input 53 to the differentiator 68, a reset pulse appears at the output of a differentiator 68 and the output of the AND-gate 65 will go to zero, turning off the OR-gate 64, breaking the holding circuit 66. When the holding circuit is ON, additional signals from the sensor 40, such as may be generated by detection of irregularities in the workpiece shape, or from switch or photocell static, will be locked out.

The trigger signal is developed at the output of the OR-gate 64 and appears at the output 54 of the trigger circuit 60 and proceeds to the input 55 of the timer circuit 70 connected to the input of a differentiator 71. The output of the differentiator 71 connects to the turn-ON input of a bi-stable switch 72 which has an output connected to the input of a delay timer 73. The delay timer 73 has an output connected to the turn- ON input of a second bi-stable switch 74 which has one of its outputs connected to the input of a duration timer 75. The output of the duration timer 75 is connected to the turn-ON" input of a third bi-stable switch 76 which has its output connected in a feedback path through a differentiator 77 to the turn-OFF input of the second bi-stable switch 74.

Another output of the second bi-stable switch 74 is connected to the output 52 of the timing circuit 70 which connects to the input of the output amplifier 80. The other outputs of the second switch 74 are connected through a differentiator 79 to the turn-OFF input of the first switch 72, and through a differentiator 78 to the turn-OFF input of the third switch 76. A delay output 56 is provided and connects to the output of the switch 72 but is not used in the illustrated embodiment.

In operation, a workpiece 11 moves along the conveyer 10 until some predetermined portion of the workpiece 11 energizes the sensor 40. Typically, this predetermined portion of the workpiece 11 will be the leading edge of workpiece 11. When the sensor 40 is energzied, a trigger signal passes through the selector gate 45 and on to the control circuit input 51 and to the trigger input 61. This trigger signal will take a form similar to that illustrated as curve (a) at time in the timing diagram at the bottom of FIG. 1. This is because the sensor 40 may respond to many points along the length of the workpiece 11 causing the sensor signal to fluctuate on and off several times before the workpiece has passed. In many cases, a burst of pulses is emitted by the sensor 40 as it is triggered on or off. This signal, curve (a), proceeds through the differentiator 63 where sharp pulses, corresponding to the leading edges of the sensor signal, are passed to the input of the OR- gate 64. The first pulse through the OR-gate 64 passes through the circuit 66 to energize the AND-gate 65. The negative input of the AND-gate 65 from the reset circuit 67 is normally in an ON state. As this first pulse through the OR-gate 64 energizes the AND-gate 65, an ON signal is fed back through the AND-gate 65 and applied to the other input of the OR-gate 64 and a closed loop is completed which holds the OR-gate 64 in the ON condition. This hold signal is illustrated by curve (b) in the timing diagram. This hold signal constitutes a trigger signal which is differentiated at the differentiator 71 to form a single pulse which proceeds to the turn-ON input of the switch 72 to turn it on. This causes the switch 72 to develop an output signal as i]- lustrated by curve (c) of the timing diagram. This signal energizes the delay timer 73. The timer 73 is adjustable and is preset to develop an output signal marking the end of a delay time period. This time delay corresponds to the time it takes a point on the workpiece 11 to move on the conveyer 10 a distance D from the position 41 adjacent the sensor 40 to a position 42. This signal, represented by curve ((1) advances to the turn-ON" input of the switch 74, which energizes the solenoid driver amplifier 80 to open the check valves 25 in accordance with curve (e) of the timing diagram.

This signal, curve (e), is also differentiated by the differentiator 79 to generate a pulse which turns off the switch 72 as curve (c) illustrates, at time t, in the timing diagram. The signal of curve (e) is also differentiated by the differentiator 78 to generate a pulse which turns off the switch 76. The switch 76 is defined in the ON state, relative to the sense of the other signals of the circuit 70, prior to the circuit 70 being triggered. The signal, curve (e), also proceeds directly to energize the duration timer 75. The duration timer 75 is, like the delay timer 73, settable to generate a pulse at some predetermined time after it has been energized. The time interval of the timer 75 corresponds to the time it takes a workpiece 11 to move from point 42 to point 43. After the elapsing of the duration interval of the timer 75, a pulse is generated at the output of the timer 75 as illustrated by curve (f) at time 1 The pulse of curve (f) proceeds to the turn-ON input of the switch 76, turning the switch 76 to the ON state at time t as illustrated by curve (g) of the timing diagram. The output of the switch 76 develops a reset signal which resets the timer circuit 70 and the trigger circuit 60. The signal, curve (g), proceeds through the differentiator 77 to the turn-OFF" input of the switch 74 to turn it off, as curve (e) illustrates. The turning off of switch 74 turns off the discharge device at time when the leading edge of the workpiece is adjacent the point 413 on the conveyer 10. The signal, curve (g) also proceeds through the differentiator 68 of the trigger circuit 60 to generate a reset pulse, illustrated by curve (h) which becomes inverted at the negative input of the AND- gate 65 to cause the AND-gate 65 to break the hold circuit through the OR-gate 64. This is represented by curve (b) in the timer diagram at time The circuit details of a control circuit 50, which performs the functions described in connection with the block diagram of FIG. 1 above, are illustrated in FIGS. 2, 3 and 4.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT The control circuit 50 as stated above includes four basic subcircuits: the trigger circuit 60, which is illustrated in detail in FIG. 2; the timer circuit 70, which is illustrated in detail in FIG. 3; the output or solenoid driver circuit 80, and a power supply circuit 90, which are both illustrated in detail in FIG. 4.

Referring first to FIG. 4, the power supply circuit 90 includes a power line 101 connectable externally to a conventional AC power line having a pair of leads 102 and 103, each connected internal of the circuit through an on-off switch 104 and 105, respectively, and a fuse 106 and 107, respoectively, to opposite terminals of a primary winding 109 of a transformer 110. The transformer 1 10 has a secondary winding 115 connected across light source 116 for a photocell. The respectively, has a core 119, which is connected to a ground line 120, and another secondary winding 121 which is isolated from the winding by an electrostatic shield 113 grounded to the core 1 19. The secondary winding 121 is connected across the input termianls 122 and 123 of a bridge rectifier 125 of the power supply rectifier and regulator circuit 126. The bridge rectifier 125 has a pair of output terminals which includes a positive output terminal 131 which provides a source of unregulated DC power, and a negative output terminal 132 which is connected to ground line 120. The output 132 is connected through a filter capacitor 129 to ground line 120. The rectifier 125 includes a first pair of diodes 133 and 134 which both have their cathodes connected to the positive output terminal 131 and each has its anodes connected to the rectifier input terminals 122 and 123, respectively. The rectifier 125 also includes a pair of diodes 137 and 138 which both have their anodes connected to the negative or ground terminal 132 and each has its cathodes connected to the input terminals 122 and 123, respectively.

A voltage regulator circuit 140 includes a resistor 141 connected in series between the rectifier output 131 and the collector 142 of an NPN transistor 143. The emitter 144 of the transistor 143 is connected to the power supply output line 145. The transistor 143 operates as a series variable impedance device which regulates the DC voltage on the output line 145. Connected between the output line 145 and the ground line 120 is a voltage divider circuit 149 which includes a fixed resistor 151, a potentiometer 152, and a fixed resistor 153 connected in series. Connected across the voltage divider 149 is a filter capacitor 154. The potentiometer 152 has a wiper contact 157 connected to the base 158 of an NPN transistor 160. The transistor 160 has its emitter 161 connected through a resistor 162 to the output line 145. The emitter 161 is also connected to the cathode of a zener diode 165 which has its anode connected to the ground line 120. A capacitor 167 is connected between the base 158 and the collector 168 of the transistor 160. The collector 168 of the transistor 160 is connected through a resistor 171 to the unregulated DC output 131, and to the base 172 of a transistor 173. The transistor 173 has its collector 174 connected to the collector 142 of the transistor 143, and its emitter 175 connected to the base 176 of the transistor 143.

Referring to FIG. 2, a photocell circuit 201, the sensor selector gate 45, a trigger circuit 60, and a trigger reset circuit 67 are illustrated.

The photocell circuit 201 includes an externally located photocell 205 having a pair of leads 206 and 207. The photocell 205, together with the light source 116 (FIG. 4) constitutes the sensor 40. A light beam make and a light beam break selector switch 208 is provided which conditions the trigger circuit to generate a trigger pulse upon either the making or breaking of the light beam to the photocell. The switch 208 is a doublepole, double-throw slide action switch having a pair of common terminals 209 and 210 which are alternatively connectable to either the regulated positive voltage line 211 as illustrated or the ground line 212. The terminal 210 connects through a resistor 215 to the photocell lead line 207. The common terminal 209 of the switch 208 is connected to the photocell lead line 206. The line 207 is connected also through a resistor 221 to the anode of a diode 222. The diode 222 has its cathode connected to the base 223 of an NPN transistor 225. A resistor 226 is connected between the base 223 of the transistor 225 and the emitter 227 of the transistor 225. The emitter 227 of the transistor 225 is connected to the wiper contact 229 of a photocell sensitivity potentiometer which forms part of a voltage divider which also includes a resistor 231 connected between one end of the potentiometer 230 and the regulated positive DC supply line 211, and a resistor 232 connected in series between the opposite end of the potentiometer 230 and the ground line 212. The collector 234 of the transistor 225 is connected through a resistor 235 to the positive line 211. The collector 234 is also connected through a filter capacitor 236 to the ground line 212 and through a resistor 237 to the base 241 of a PNP transistor 242. Base 241 of the transistor 242 is also connected to a resistor 243 to the positive line 211. The emitter 245 of the transistor 242 is connected to the cathode of a diode 246 which has its anode connected to the cathode of a diode 244. The diode 244 has its anode connected to the positive line 211. The collector 247 of the transistor 242 is connected through a resistor 248 to the common line 212. A resistor 250 is connected between the emitter 245 of transistor242 and the ground line 212.

The input gate 45 is provided with four inputs 44 consisting of the anodes of diodes 251 through 254, respectively. The anode of diode 251 is the photocell input and is connected to collector 247 of the transistor 242. The anode of diode 252 is the normally closed switch input and is connected to the common contact 255 of the normally closed switch 256 which has its normally closed contact 257 connected to the ground line 212. The anode of diode 252 is also connected through a resistor 259 to the positive DC line 21 1. The anode of diode 253 provides the normally open switch input and is connected through a resistor 261 to the ground 212 and through a resistor 262 to a normally opened contact 263 of the normally opened switch 264. The common terminal of the switch 264 is connected to the positive voltage line 211. The anode of diode 254 is connectable to a proximity switch (not shown). The cathodes of diodes 251-254 are connected together at the gate output terminal 268. A fifth test input is provided which includes a resistor 271 connected between the gate output 268 and one contact 272 of a momentary push button test switch 273. The other contact 274 of the switch 273 is connected to one contact 275 of a test operate switch 276. The common terminal of 277 of the switch 276 is connected to the unregulated DC power line. The other contact 278 is connected to the output of circuit 80 (FIG. 4). Connected between the terminal 275 of the switch 276 and the ground line 212 is a test indicator lamp 279 connected in series with a resistor 280.

The gate output 268 is connected to the input 61 of the trigger circuit 60 and the differentiator 63. The input 61 is connected through a resistor 302 to the ground 212, and through a capacitor 307 to the anode of a diode 301. Connected in series between the cathode of the diode 301 and the base 305 of an NPN transistor 306, is a resistor 308. The anode of diode 301 is connected through a resistor 310 to ground line 212 and to the cathode of a diode 311 which has its anode connected to ground line 212. The base 305 of the transistor 306 is connected through a resistor 312 to a ground line 212.

The emitter 313 of the transistor 306 is connected through a resistor 314 to the ground line 212 and through a resistor 315 to the positive voltage line 211. The collector 317 of the transistor 306 is connected through a resistor 318 to the positive line 211 and through a resistor 319 to the base 321 of a PNP transistor 322. The emitter 323 of the transistor 322 is connected through a resistor 324 to the ground line 212 and to the cathode of a diode 327, which in turn has its anode connected to the cathode of a diode 328, which has its anode connected to the positive voltage line 211. The collector 331 of the transistor 322 is connected to a resistor 332 to the trigger circuit output line 54. The output line 54 is connected through a resistor 341 to the ground line 212. The circuits of the transistors 306 and 322 generally make up the OR-gate 64.

The trigger output line 54 is also connected through the holding circuit 66, which is connected through a resistor 344 to the anode of a diode 345. The diode 345 has its cathode connected to the base 305 of the transistor 306.

A trigger reset circuit includes an N PN transistor 350 having its emitter 351 connected to the ground line 212 and its collector 352 connected to the trigger circuit output line 54. The base 353 of the transistor 350 is connected to a resistor 354 to the ground line 212 and through a series circuit consisting of a resistor 355 and a capacitor 356 to the positive voltage line 211. The base 353 of the transistor 350 is also connected through a resistor 361 to the cathode of a diode 362 which has its anode connected to the ground line 212. A capacitor 365 is connected between the cathode or diode 362 and the reset input line 53. The capacitor 365, the resistors 354 and 361, and the diode 362 make up the differentiator 68.

Referring now to FIG. 3, the timing circuit 70 has a positive regulated voltage line 401 and a ground line 402. A diode-resistor voltage divider 402 having a first diode 405 connected at its anode to the positive voltage line 401 and its cathode to the anode of a diode 406 which in turn has its cathode connected through resistor 407 to the common ground line 402. At the juncture of the diode 406 and the resistor 407 is connected a charging voltage line 409.

The input 55 of the timing circuit is connected to the output 54 of the trigger circuit 60 of FIG. 2. The input 55 is connected through the differentiator 71, which includes a capacitor 411 connected to the turn- ON" input 412 of the switch 72, which is connected through a resistor 413 to the ground line 402, and to the anode of a diode 415.

The cathode of the diode 415 is connected to the gate 417 of an SCR 418. The SCR has its anode 419 connected to the positive voltage line 401 and its cathode 420 connected through diode 422 to the delayed signal line 425, which is the output of the switch circuit 72. The cathode 420 of the SCR 418 is connected through a resistor 431 to the SCR gate 417. The cathode 420 is also connected to the cathode of a diode 432 which has its anode connected to the ground line 402.

The delay signal line 425 is connected to the input 434 of a delay signal lamp illuminating circuit 435. The

lamp illuminating circuit 435 includes a resistor 436 connected between the input 434 and a ground line 437, which is in turn connected to the ground line 402. The input 434 is also connected through a resistor 439 to the base 440 of an NPN transistor 441 which has its collector 442 connected to an unregulated positive DC voltage line 445, and its emitter 446 connected through a delay indicator lamp 447 to the ground line 437. The voltage line 445 is connected through a resistor 449 to the unregulated positive voltage line 131 of the power supply 126 (P16. 4).

The delay signal, curve (c) of FIG. 1 table, on line 425 is also connected to the input of the delay timer circuit 73 through a variable resistor 451 and a fixed resistor 452 to ground. The variable resistor 45! provides a means to adjust the turn-ON" threshold of the timer 73 and to calibrate the timer dial set forth below. The timer circuit 73 is a unijunction relaxation oscillator circuit. The junction of the resistors 451 and 452 is connected through a resistor 453 to the base-two terminal 455 of a unijunction transistor 456. The emitter 457 of the unijunction transistor 456 is connected to the collector 461 of a PNP transistor 462, and through a capacitor 463 to the ground line 402. Connected across the capacitor 463 through a switch 464 is a capacitor 465. This provides a means for selecting the range of time delays which the timer 73 can produce. With the switch 464 closed. longer delays are possible.

The circuitry associated with the transistor 462 provides a constant current charging circuit for the capacitors 463 and 464. The transistor 462 has its base 466 connected through a resistor 467 to ground line 402, and through a resistor 468 to the cathode of a diode 469. The anode of the diode 469 is connected to the charging circuit voltage line 409. Connected between the voltage line 409 and the emitter 470 of the transistor 462 is a fixed resistor 471 and a variable resistor 472. The variable resistor 472 is provided with an externally accessible dial 474 which permits adjustment of the delay of the output signal of the timer circuit 73. By use of this constant current charging circuit. an exceptionally wide range of settings is possible by continuous adjustment of the single variable resistor 472. The delay interval is measured from the time at which the timer 73 is energized through its input at the resistor 45]. A delay signal output 56, unused in the present embodiment, is provided and connects with the line 425.

Between the base-one terminal 481 of the unijunction transistor 456 and the ground line 402 is connected a resistor 482. The delay signal output, curve (d), is developed at the base-one termianl 481 of the unijunction transistor 456 which is connected to the end-delay output line 483. The line 483 is connected to the anode of the diode 485 which has its cathode connected to the gate 487 of an SCR 488. The diode 485 is the turn-ON input of the SCR switch 74. The SCR gate 487 is connected through resistor 484 to the SCR cathode 490. The SCR 488 has its anode 489 connected to the positive voltage line 401 and its cathode 490 connected to the duration signal line 495 which is the output of the switch circuit 74. The signal on line 495 is illustrated by curve (e) of the table of FIG. 1. The cathode 490 of SCR 488 is also connected to the cathode of a diode 486 which has its anode connected to the ground line 402.

The line 495 is also connected through the differentiator circuit 79 to the delay signal line 425, which serves as the turn-OFF" input of the switch circuit 72. The differentiator circuit 79 includes a diode 497 having its anode connected to the cathode 490 of the SCR 488 and its cathode connected through a capacitor 498 to the delay signal line 425, and through a resistor 499 to the ground line 402.

The duration line 495 is also connected to the input 501 of a lamp driver circuit 502. The input 501 of the circuit 502 is connected through a resistor 503 to the ground line 437, and through a resistor 504 to the base 507 of an NPN transistor 508. The collector 509 of the transistor 508 is connected to the unregulated DC line 445, and the emitter 510 of the transistor 508 is connected through the duration indicator light 513 to the ground line 437.

The duration signal, curve (e) of FIG. 1, on line 495 is also connected to the input of the duration timer circuit through a variable resistor 551 and a fixed resistor 552 to ground. The variable resistor 551 provides a means to adjust the turn-ON" threshold of the timer 75 and to calibrate the timer dial set forth below. The timer circuit 75 is a unijunction relaxation oscillator circuit similar to the delay timer circuit 73. The junction of the resistors 551 and 552 is connected through a resistor 553 to the base-two terminal 555 of a unijunction transistor 556. The emitter 557 of the uniju nction transistor 556 is connected to the collector 561 of a PNP transistor 562 and through a capacitor 563 to the ground line 402. Connected across the capacitor 563 through a switch 564 is a capacitor 565. This provides a means for selecting the range of time delays which the timer 75 can produce.

A constant current charging circuit for the capacitors 564 and 565 includes the transistor 562 which has its base 566 connected through a resistor 567 to ground line 402 and through a resistor 568 to the cathode of a diode 569. The anode of the diode 569 is connected to the charging circuit voltage line 409. Connected between the voltage line 409 and the emitter 570 of the transistor 562 is a fixed resistor 571 ana variable resistor 572. The variable resistor 572 is provided with an externally accessible dial 574 which permits adjust ment of the delay of the output signal of the timer circuit 75. This delay is measured from the time at which the timer 75 is energized through its input at the resistor 551. Between the base-one terminal 581 of the unijunction transistor 556 and the ground line 402 is connected a resistor 582. The duration signal output, curve (f) is developed at the base-one terminal 581 of the unijunction transistor 556 which is connected to the end-duration output signal line 583. The line 583 is connected to the anode of the diode 585 which has its cathode connected to the gate 587 of an SCR 588. The diode 585 is the turn-ON input of the SCR switch 76. The gate 587 of SCR 588 is connected through resistor 584 to the SCR cathode 590. The SCR 588 has its anode 589 connected to the positive voltage line 401 and its cathode 590 connected to the reset output line 58 which connects to the reset input 53 of the trigger circuit 60. The signal on line 58 is illustrated by curve (g) of the table of FIG. 1. The cathode 590 of SCR 588 is also connected to the cathode of a diode 596, in line 595, which has its anode connected to the ground line 402.

The line 595 is also connected through the differentiator circuit 77 to the duration signal line 495, which serves as the tum-OFF" input of the switch circuit 74. The differentiator circuit 77 includes a diode 597 having its anode connected to the cathode 590 of the SCR 588 and its cathode connected through a capacitor 598 to the duration signal line 495 and through a resistor 599 to the ground line 402. The differentiator circuit 77 also forms the differentiator 78 when operating in the reverse direction to transmit a pulse from line 495 to the cathode 590 of SCR 588 to turn it off.

Referring again to FIG. 4, the output or solenoid driver circuit 80 has an input 81 which is connected to the output 52 of the timing circuit 70. The driver circuit 80 has a positive DC line 602 which is connected to the operate contact 278 of the test-operate switch 276 which has its common terminal 277 connected to the unregulated DC output 131 of the power supply 90. The switch 276 is also illustrated in the circuit of FIG. 2. The output circuit 80 is also provided with a ground line 604. The outputs of the output circuit are the windings 603 of the solenoid valves 25.

The input 581 of the output circuit 80 is connected through a resistor 611 to the base 612 of an NPN transistor 613, which has its emitter 614 connected to the base 616 of an NPN transistor 617, which in turn has its emitter 618 connected to the ground line 604. The collector 621 of the transistor 613, and the collector 622 of the transistor 617, are connected to a bus line 625. The bus line 625 is connected to one terminal 627 of each of the windings 603 of the solenoid valves 25. The other terminal 628 of each of the windings 603 of the solenoid valves 25 is connected through a different one of the resistors 631 to the ground line 604. Across each of the resistors 631 is a capacitor 632. The terminals 628 of the windings 603 are each connected through one of a set of resistors 637 to the positive unregulated line 602. The terminals 628 to windings 603 are also each connected to the cathodes of one of diodes 638. Each of the diodes 638 has its anodes connected to the bus line 625. The terminals 627 and 628 of the solenoid windings 603 constitute the outputs 82 of the driver circuit 80.

The output circuit 80 combines two important features. The first is a rapid solenoid pull-in feature provided by the capacitors 632 which charge to a higher voltage than is required to pull-in the solenoids 603, when the output circuit is off, and provide additional overvoltage current to accelerate the initial pull-in of the solenoids 603 at the instant the transistor 617 is actuated. The second feature is that of short circuit protection provided by the resistors 637.

CIRCUIT OPERATION The specific operation of the timer circuit 50 will be better understood by tracing a signal through the circuit of FIGS. 2-4, for the case where the sensor signal is generated by the making of a light beam.

As illustrated in the drawing of FIG. 2, the photocell 205 will generate a signal upon the making of a light beam. This signal will be reflected in the circuit by a decrease of impedance of the photocell 205. With the switch 208 set as shown in FIG. 2, the signal on the base 223 of transistor 225 is normally below the level of the emitter 227 as determined by the setting of the sensitivity potentiometer 229, rendering the transistor 225 non-conductive. The signal from the photocell causes the base 223 of the transistor 225 to go positive, relative to the emitter 227, switching the transistor 225 ON, causing a decreasing voltage to appear at the collector 234 of the transistor 225. The capacitor 236 filters out high frequency noise from this collector signal. The switching ON of the transistor 225 also switches ON the transistor 242 to cause a positive going voltage to be applied through the diode 251 to the differentiator 63. The differentiator 63 transmits a positive pulse, corresponding to the leading edge of this positive going voltage, to the base 305 of the transistor 306, causing it to switch ON. This applies a negative voltage to the base 321 of transistor 322 which in turn applies a positive voltage to line 55. This positive voltage on line 55 is the trigger signal. This positive voltage is fed back from the line 55 through the hold circuit 66 to the base ofthe transistor 305. Thus, once the transistor 305 is turned ON, it latches itself in the ON state until the hold circuit 66 is broken, thus holding the trigger signal on line 55 in the ON state.

The signal on the line 55 is differentiated by the differentiator 71 to transmit a single positive pulse, corresponding to the leading edge of the trigger signal, to'the turn-ON input of the first SCR switch 72 at the gate 417 of the SCR 418. This causes the SCR to switch ON and to continuously conduct to energize the line 425 during the delay interval.

Normally, when SCR 418 is OFF, the line 425 and consequently the base-two terminal 455 of the UJT 456 is at a low voltage state, which allows the constantcurrent output from the collector 461 of transistor 462 to be grounded through the emitter base-one of the UJT 456 and resistor 482, discharging capacitor 463 (and capacitor 465). This develops some initial low voltage on the capacitors 463 and 465 as determined by the setting of the resistor 451.

The voltage on line 425 energizes the timer circuit 73 through the resistor 451. This allows the capacitor 463 to begin to charge at a predetermined rate by a constant current controlled by the setting of the delay interval control resistor 472. (If the switch 464 is closed to connect the capacitor 465 across the capacitor 463, much longer charging times will be selected). When the capacitor has charged to the point determined by the combined settings of resistors 451 and 472, where the voltage at the emitter 457 of the unijunction 456 reaches the break-over voltage of the unijunction transistor, the unijunction transistor 456 will conduct, causing a momentary positive voltage to appear across the resistor 483. This momentary voltage or pulse marks the end of the delay interval and the beginning of the duration interval in which the spray apparatus is to be operating. This momentary voltage appears as a positive pulse at the gate of the SCR 488 and causes the SCR 488 to conduct. This applies a positive voltage to the line 495 which, differentiated through the capacitor 498, applies a positive pulse to the base of SCR 418, reverse biasing SCR 418 and turning it off. This disables the timer 73. It is noted that the trigger signal on line 55 is still in the ON condition.

The signal on line 495 is conducted through the output line 52 to the input line 81 of the output circuit 80. This applies a positive signal to the base of the transistors 613 and in turn to the base of transistor 617, causing the transistor 617 to ground the line 625 to line 604. This causes the capacitors 632, which are normally maintained in a charged state, to discharge through the solenoid windings 603. The capacitors 632 are normally charged with a higher voltage than is necessary to energize the windings 603 and one of large enough capacity to supply ample current to very rapidly energize the windings 603. The windings 603 remain energized through the resistors 637 until the signal at the input line 81 is removed, de-energizing the transistors 613 and 617. The resistors 637 limit the output current to the windings 603 in the event that their terminals become shorted, thus protecting the output transistor 617.

The positive signal on line 495 is transmitted through the differentiator 78 to backward bias the SCR 588 to turn it off. The SCR 588 will have remained on from the previous trigger signal.

The positive voltage on line 495 further energizes the timer 75, which causes the capacitor 563 to charge at a rate controlled by the setting of the variable resistor 572. After a period of time representative of the duration time interval, the unijunction transistor 556 conducts, discharging the capacitor 563 through the resistor 582, causing a momentary positive pulse to appear on line 583. This pulse is applied to the gate 587 of the SCR 588 to turn on the SCR switch 76. The turning on of the SCR switch 76 generates a positive going signal which is differentiated at the differentiator 77 to apply a positive pulse to line 495 which backward biases the SCR 488, turning it off. This removes the voltage from output line 52, turning off transistors 613 and 617 and tie-energizing the windings 603.

Also, the turning ON of the SCR 588 generates a positive going signal on line 58 which is differentiated by the differentiator 68 in FIG. 2 to apply a positive going pulse to the base 353 of the transistor 350, causing it to conduct, shunting the holding circuit 66 to ground. If the sensor signal has returned to normal, this reset signal removes the base current from the transistor 306, turning OFF the trigger signal output until the next signal is received from the sensor.

PLURAL TIMER EMBODIMENTS FIGS. 5 and 6 illustrate control systems in which a plurality of timers 70 are connected sequentially to provide multiple time intervals. In this way, different coating devices can be made to operate at different times during a coating cycle. The diagrams of FIGS. 5 and 6 illustrate two alternative means for programming plural outputs differently in accordance with different combinations of outputs from the timers 70.

Referring specifically to FIG. 5, the input 61 of the trigger circuit 60 connects from the output 46 of thesensor selector gate 45. The output 54 of the trigger circuit 60 connects to the input 55A of the first timer circuit 70A. The reset output 58A from the timer 70A connects to the input 558 of the timer 7013. The reset output 588 of the timer 70B connects to the reset input 53 of the trigger circuit 60. The timer 70A and 70B are identical to the circuit of the timer 70, illustrated in FIG. 3. Each has a delay output line 56A and 56B, respectively, and a duration output line 52A and 52B, respectively. A pair of output circuits 80A and 80B are provided, each having sets of outputs 82A and 8213, respectively, connecting to difierent solenoid valves, which control different discharge devices. The output circuits 80A and 80B are as illustrated in FIG. 4. Each of the outputs 80 has a respective input 81A and 818 which is connected to the output of an OR-gate 701A and 7018. Each of the OR-gates has a plurality of inputs 702A and 702B, respectively. Each of the inputs is connected through a different one of a plurality of switches 703 to one of the outputs 56A, 56B, 52A, and 52B of the timers. By selectively closing the various ones of the switches 703, the output circuit 80 can be actuated during any of four time intervals during each of the cycles.

Similarly, a circuit of FIG. 6 illustrates a control system in which three timers A, 70B, and 70C are connected sequentially. In a similar manner. the reset outputs 58A and 58B of each of the circuits connects to the input 55B and 55C of the next succeeding timer circuit, with the reset output 58C of the timer 70C being connected to the reset input 53 of the trigger board 60. The delay and duration outputs 56 and 52 are each connected to the anodes of different ones of the diodes 711, which have cathodes connected to a different one of the conductors of a first set of conductors 715. A second set of conductors 716 is provided which connects to an input of a different one of a plurality of output circuits 80. The conductors 715 and 716 in the embodiment illustrated are in matrix form. In this combination, six output intervals can be programmed for each cycle, and any number of output units can be selectively programmed to be actuated during any one of the six output intervals. To program the outputs 80, the corresponding conductors of the set 716 are electrically connected by the use of connectors, switches, or other means to the conductors of the set 715 which correspond to the desired interval output from the timer 70, during which it is desired to actuate the outputs 80.

In addition to the combinations of timers 70 illustrated in FIGS. 5 and 6, it will be apparent from the present specification that various other combinations can be employed.

As an example of the operation of the combination of timers, the circuit illustrated in FIG. 6, when programmed, is illustrated in that figure with each of the dots 719 representing the contact points between the respective conductors 715 and 716. The operation can be readily understood from the timing diagram at the left of FIG. 6, in which the curves (j,) through (j represent the outputs of the respective output circuits 80A through 80D, while the curves (at) through (h represent signals corresponding in operational detail to those illustrated in the timing diagram of FIG. 1 in connection with the single timer control system, and correspond to the respective timers I through 3.

EMBODIMENT FOR CLOSED WORKPIECE SPAClNG When the objects to be coated are fed with exceptionally close spacing, it may be desireable to overlap the delay and duration intervals for the purpose of speeding up the coating operation. When this is desired, the holding circuit 66 (FIGS. 1 and 2), or perhaps even the entire trigger circuit 60 may be eliminated. In this case, the first solid state switch 72 will perform the trigger signal lock-out function during the delay interval and will be reset at the end of the delay interval. In such a way, the timer circuit 70 is in a condition to accept the next succeeding sensor signal while the duration interval is proceeding. In such cases some minor circuit modification may be necessary within the timer circuit 70 (FIG. 3). For example, it has been vent effecting the duration interval when SCR 488isturned ON by, for example, premature turn-OFF of SCR 488. For such a purpose, an additional SCR has been incorporated successfully into the differentiator 79, with its cathode to the junction of capacitor 498 and resistor 499, and its anode connected to line 401. Diode 497 was disconnected and re-connected with its cathode connected to the gate of this additional SCR and its anode connected to the base-one terminal 481 of UJT 456.

We claim:

1. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising:

a bi-stable trigger circuit having a set" input for receiving said input signal, a reset" input for receiving a reset signal, and an output;

a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval;

said trigger circuit comprising:

a. first and second DC power leads, including a positive and a negative lead;

b. a first and a second transistor, including a PNP and an NPN transistor;

0. said first transistor having its base connected to said set input and its emitter to said first lead;

d. a first resistor connected between the collector of said first transistor and said second lead;

e. said second transistor having its base connected to the collector of said first transistor, and its collector connected to said trigger output;

f. a second resistor connected between the collector of said second transistor and said first lead;

g. a diode connected between the emitter of said second transistor and said second lead; and

h. a third transistor having its base connected to said reset input, and having its collector and emitter connected between the base of said first transistor and said first lead.

2. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising:

a bi-stable trigger circuit having a set" input for receiving said input signal, a reset input for receiving a reset signal, and an output;

a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval;

said timer circuit comprising:

a. positive and negative DC power leads;

b. a third lead including means for connecting said third lead to said positive lead;

c. first, second and third SCRs;

d. first and second UJTs;

e. first and second PNP transistors;

f. said first SCR having its gate connected to said timer input, its anode connected to said positive lead and its cathode connected to said delay output;

g. a first resistor connected between the base-one termianl of said first UJT and said negative lead;

h. a first variable resistor connected between the base-two termianl of said first UJT and said delay output;

i. a first capacitor connected between the emitter of said first UJT and said negative lead;

j. a second variable resistor connected between the emitter of said first transistor and said third lead;

k. the collector of said first transistor being connected to the emitter of said first UJT;

l. a voltage divider connected between said third lead and said negative lead, and having an intermediate'point connected to the base of said first transistor;

m. said second SCR having its gate connected to the base-one terminal of said first UJT, its anode connected to said positive lead and its cathode connected to said duration output;

n. a second resistor connected between the baseone terminal of said second UJT and'said negative lead;

0. a third variable resistor connected between the base-two terminal of said second UJT and said duration output;

p. a second capacitor connected between the emitter of said second UJT and said negative lead;

q. a fourth variable resistor connected between the emitter of said second transistor and said third lead;

. the collector of said second transistor'being connected to the emitter of said second UJT;

. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said second transistor; and

t. said third SCR having its gate connected to the base-one terminal of said second UJT and its anode connected to said positive lead.

3. A control circuit according to claim 2 further comprising:

a third capacitor connected between the cathodes of said first and second SCRs; and

a fourth capacitor connected between the cathodes of said second and thirds SCRs.

4. A control circuit according to claim 3 further comprising:

a fifth capacitor connected between said timer input and the gate of said first SCR; and

a sixth capacitor connected between the cathode of b. a first and a second transistor, including a PNP and an NPN transistor;

c'. said first transistor having its base connected to said set input and its emitter to said first lead; d. a first resistor connected between the collector of said first transistor and said second lead;

e. said second transistor having its base connected to the collector of said first transistor and its collector connected to said trigger output;

f. a second resistor connected between the collector of said second transistor and said first lead;

g. a diode connected between the emitter of said second transistor and said second lead; and h. a third transistor having its base connected to said reset input, and having its collector and emitter connected between the base of said first transistor and said first lead.

7. A control circuit according to claim 2 further comprising:

a power output circuit having a". a pair of output leads;

b". a pair of DC power leads; c". a capacitor connected between one of said output leads and one of said power leads; d". a resistor connected between said one of said output leads and the other of said power leads; e a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and

f". said power transistor having its base connected to an output of said timer circuit.

8. A timer circuit according to claim 7 further comprising:

a second transistor having its collector connected to the collector of said power transistor, its emitter connected to the base of said power transistor, and its base connected to said output of said timer circuit.

9. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising:

a bi-stable trigger circuit having a set" input for receiving said input signal, a reset" input for receiving a reset signal, and an output;

a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; and

a power output circuit having a". a pair of output leads;

b". a pair of DC power leads; c a capacitor connected between one of said output leads and one of said power leads; d". a resistor connected between said one of said output leads and the other of said power leads; e". a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and

f". said power transistor having its base connected to an output of said timer circuit.

10. A timer circuit according to claim 9 further comprising:

a second transistor having its collector connected to the collector of said power transistor, its emitter connected to the base of said power transistor, and its base connected to said output of said timer circuit.

11. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising:

a delay-duration interval timer circuit having an input connected for receiving said input signal, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval;

said timer circuit comprising:

a. positive and negative DC power leads;

b. a third lead including means for connecting said third lead to said positive lead;

c. first, second and third SCRs;

d. first and second UJTs;

e. first and second PNP transistors;

f. said first SCR having its gate connected to said timer input, its anode connected to said positive lead and its cathode connected to said delay output;

g. a first resistor connected between the base-one terminal of said first UJT and said negative lead;

h. a first variable resistor connected between the base-two terminal of said first UJT and said delay output;

i. a first capacitor connected between the emitter of said first UJT and said negative lead;

j. a second variable resistor connected between the emitter of said first transistor and said third lead;

k. the collector of said first transistor being connected to the emitter of said first UJT;

l. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said first transistor;

in. said second SCR having its gate connected to the base-one terminal of said first UJT, its anode connected to said positive lead and its cathode connected to said duration output;

n. a second resistor connected between the baseone terminal of said second UJT and said negative lead;

0. a third variable resistor connected between the base-two terminal of said second UJT and said duration output;

p. a second capacitor connected between the emitter of said second UJT and said negative lead;

q. a fourth variable resistor connected between the emitter of said second transistor and said third lead;

. the collector of said second transistor being connected to the emitter of said second UJT;

. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said second transistor; and

. said third SCR having its gate connected to the base-one terminal of said second UJT and its anode connected to said positive lead.

12. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising:

put leads and one of said power leads; d". a resistor connected between said one of said output leads and the other of said power leads; e a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and

f said power transistor having its base connected to an output of said timer circuit. 

1. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a bi-stable trigger circuit having a ''''set'''' input for receiving said input signal, a ''''reset'''' input for receiving a reset signal, and an output; a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; said trigger circuit comprising: a. first and second DC power leads, including a positive and a negative lead; b. a first and a second transistor, including a PNP and an NPN transistor; c. said first transistor having its base connected to said ''''set'''' input and its emitter to said first lead; d. a first resistor connected between the collector of said first transistor and said second lead; e. said second transistor having its base connected to the collector of said first transistor, and its collector connected to said trigger output; f. a second resistor connected between the collector of said second transistor and said first lead; g. a diode connected between the emitter of said second transistor and said second lead; and h. a third transistor having its base connected to said ''''reset'''' input, and having its collector and emitter connected between the base of said first transistor and said first lead.
 2. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a bi-stable trigger circuit having a ''''set'''' input for receiving said input signal, a ''''reset'''' input for receiving a reset signal, and an output; a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; said timer circuit comprising: a. positive and negative DC power leads; b. a third lead including means for connecting said third lead to said positive lead; c. first, second and third SCRs; d. first and second UJTs; e. first and second PNP transistors; f. said first SCR having its gate connected to said timer input, its anode connected to said positive lead and its cathode connected to said delay output; g. a first resistor connected between the base-one termianl of said first UJT and said negative lead; h. a first variable resistor connected between the base-two termianl of said first UJT and said delay output; i. a first capacitor connected between the emitter of said first UJT and said negative lead; j. a second variable resistor connected between the emitter of said first transistor and said third lead; k. the collector of said first transistor being connected to the emitter of said first UJT; l. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said first transistor; m. said second SCR having its gate connected to the base-one terminal of said first UJT, its anode connected to said positive lead and its cathode connected to said duration output; n. a second resistor connected between the base-one terminal of said second UJT and said negative lead; o. a third variable resistor connected between the base-two terminal of said second UJT and said duration output; p. a second capacitor connected between the emitter of said second UJT and said negative lead; q. a fourth variable resistor connected between the emitter of said second transistor and said third lead; r. the collector of said second transistor being connected to the emitter of said second UJT; s. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said second transistor; and t. said third SCR having its gate connected to the base-one terminal of said second UJT and its anode connected to said positive lead.
 3. A control circuit according to claim 2 further comprising: a third capacitor connected between the cathodes of said first and second SCRs; and a fourth capacitor connected between the cathodes of said second and thirds SCRs.
 4. A control circuit according to claim 3 further comprising: a fifth capacitor connected between said timer input and the gate of said first SCR; and a sixth capacitor connected between the cathode of said third SCR and the ''''reset'''' input of said trigger circuit.
 5. A control circuit according to claim 2 further comprising: a first diode connected in said voltage divider between said third lead and said intermediate point; and said third lead connecting means including a second diode connected between said positive lead and said third lead.
 6. A control circuit according to claim 2 wherein said trigger circuit comprises: a''. first and second DC power leads, including a positive and a negative lead; b''. a first and a second transistor, including a PNP and an NPN transistor; c''. said first transistor having its base connected to said ''''set'''' input and its emitter to said first lead; d''. a first resistor connected between the collector of said first transistor and said second lead; e''. said second transistor having its base connected to the collector of said first transistor and its collector connected to said trigger output; f''. a second resistor connected between the collector of said second transistor and said first lead; g''. a diode connected between the emitter of said second transistor and said second lead; and h''. a third transistor having its base connected to said ''''reset'''' input, and having its collector and emitter connected between the base of said first transistor and said first lead.
 7. A control circuit according to claim 2 further comprising: a power output circuit having a''''. a pair of output leads; b''''. a pair of DC power leads; c''''. a capacitor connected between one of said output leads and one of said power leads; d''''. a resistor connected between said one of said output leads and the other of said power leads; e''''. a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and f''''. said power transistor having its base connected to an output of said timer circuit.
 8. A timer circuit according to claim 7 further comprising: a second transistor having its collector connected to the collector of said power transistor, its emitter connected to the base of said power transistor, and its base connected to said output of said timer circuit.
 9. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a bi-stable trigger circuit having a ''''set'''' input for receiving said input signal, a ''''reset'''' input for receiving a reset signal, and an output; a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; and a power output circuit having a''''. a pair of output leads; b''''. a pair of DC power leads; c''''. a capacitor connected between one of said output leads and one of said power leads; d''''. a resistor connected between said one of said output leads and the other of said power leads; e''''. a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and f''''. said power transistor having its base connected to an output of said timer circuit.
 10. A timer circuit according to claim 9 further comprising: a second transistor having its collector connected to the collector of said power transistor, its emitter connected to the base of said power transistor, and its base connected to said output of said timer circuit.
 11. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a dElay-duration interval timer circuit having an input connected for receiving said input signal, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; said timer circuit comprising: a. positive and negative DC power leads; b. a third lead including means for connecting said third lead to said positive lead; c. first, second and third SCRs; d. first and second UJTs; e. first and second PNP transistors; f. said first SCR having its gate connected to said timer input, its anode connected to said positive lead and its cathode connected to said delay output; g. a first resistor connected between the base-one terminal of said first UJT and said negative lead; h. a first variable resistor connected between the base-two terminal of said first UJT and said delay output; i. a first capacitor connected between the emitter of said first UJT and said negative lead; j. a second variable resistor connected between the emitter of said first transistor and said third lead; k. the collector of said first transistor being connected to the emitter of said first UJT; l. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said first transistor; m. said second SCR having its gate connected to the base-one terminal of said first UJT, its anode connected to said positive lead and its cathode connected to said duration output; n. a second resistor connected between the base-one terminal of said second UJT and said negative lead; o. a third variable resistor connected between the base-two terminal of said second UJT and said duration output; p. a second capacitor connected between the emitter of said second UJT and said negative lead; q. a fourth variable resistor connected between the emitter of said second transistor and said third lead; r. the collector of said second transistor being connected to the emitter of said second UJT; s. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said second transistor; and t. said third SCR having its gate connected to the base-one terminal of said second UJT and its anode connected to said positive lead.
 12. A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a delay-duration interval timer circuit having an input connected for receiving said input signal, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; and a power output circuit having a''''. a pair of output leads; b''''. a pair of DC power leads; c''''. a capacitor connected between one of said output leads and one of said power leads; d''''. a resistor connected between said one of said output leads and the other of said power leads; e''''. a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and f''''. said power transistor having its base connected to an output of said timer circuit. 